Common mode rejection ratio is the ability for a device to reject or suppress “common mode noise” -that is noise that is common(identical) to both differential input channels. Let’s take an opamp for example with an audio signal at its differential(inverting and non inverting) inputs.


Since a differential amplifier amplifies the difference between the two signals, even if it’s located in an area with a lot of interference you should have suppression of such interference because for common mode signals, this difference is zero. Such is the case with a high CMRR. However If the opamp has a very poor CMRR or the layout contributes to a poor CMRR then some of that interference will end up getting amplified along with the audio signal and appear on the output. No good.

An example of a common mode noise source may be EMI from a nearby switching power supply or transformer since this noise could appear simultaneously on both inputs. CMRR is typically represented in “db” and the higher the number, the better ability it has to attenuate the common mode noise. Differential mode gain over common mode gain=CMRR. So to have a high CMRR would require there to be a really high differential gain and really low common mode gain.

What can you do to improve the common mode rejection ratio?

Aside from choosing a high quality IC that has high precision matched internal resistance on the differential inputs, there are some additional things you can do to make sure this is as high as possible. For one thing, if you are using an RC filter network before the inputs it should be as closely matched between the differential inputs of the opamp/amp as possible. Choosing resistors with the lowest percent tolerance possible will greatly benefit CMRR as both channels will be more closely matched. This will usually mean using thin film resistors in a Surface mount technology opposed to through hole resistors since the former is available in more strict of a tolerance than the latter. Another thing you can do is similar to what you would do in high speed or critical timing routing, such as with DDR memory layout, at least in regards to matching the input trace lengths since they also contribute a small amount to the resistance and inductance. Additional things such as making sure the plane underneath the trace routing to the input pins is identical between both is also beneficial. For instance, if you are going to use a ground plane then make sure it’s underneath both of the traces and not just 1. This is because having both traces capacitively coupled to ground would keep things common between inputs, and any external noise sources would have a common effect. Having only 1 capacitively coupled to ground could cause variances between the 2 signals and external noise sources could have a different effect between them.

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